1. Field of the Invention
The present invention relates to a semiconductor integrated circuit for transmitting a data signal from a core on the transmitter side to a core on the receiver side inside a fine-process adopted LSI.
2. Description of the Prior Art
Conventionally, when a data signal is transmitted from a core (circuit) on the transmitter side to a core (circuit) on the receiver side inside an LSI, a clock is distributed from the same source point to both the transmitter-side core and the receiver-side core to allow flipflops (FFs) in the transmitter-side and receiver-side cores to operate synchronously. This operation scheme however has a problem as follows when the operation is made at high speed with a clock frequency of several GHz or more. That is, a data signal will not be transmitted correctly if the sum of the delay time of the FF in the transmitter-side core, the wiring delay time between the cores and the setup time of the FF in the receiver-side core fails to be equal to or less than the period of one cycle of the clock.
To solve the above problem, disclosed is a semiconductor integrated circuit in which a transmitter-side LSI transmits a source clock simultaneously with data via the same transmission line, and a receiver-side LSI samples the data with the source clock and then synchronizes the sampled data with a clock in the receiver-side LSI, to thereby suppress variations in the delay time of the transmission line and occurrence of clock skew (see Japanese Laid-Open Publication No. 2000-347993, for example, which is hereinafter referred to as Patent Document 1)
As another example, a semiconductor integrated circuit as follows is disclosed (see Japanese Laid-Open Publication No. 2001-195354, for example, which is hereinafter referred to as Patent Document 2). This semiconductor integrated circuit has a transmission line provided between a transmitter-side LSI and a receiver-side LSI for simultaneous transmission of a plurality of data units and a clock. The semiconductor integrated circuit also has a sampling means for sampling data transmitted via the transmission line with the clock transmitted via the transmission line. The sampled data is synchronized with the system clock in the receiver-side LSI.
However, the conventional technique disclosed in Patent Document 1 has the following problem. When a data signal is transmitted at high speed in a fine-process adopted semiconductor integrated circuit, it is difficult to secure the eye pattern of the signal.
For example, as the process is made finer, the transistor gate length becomes smaller and as a result the signal wiring length in a block becomes shorter. Therefore, although the sheet resistance and coupling capacitance of a fine layer used for wiring in the block increase, the performance can be maintained. However, since the total number of hard macros and processors mounted in an LSI increases, the chip area of the LSI becomes roughly the same as the area of a conventional LSI that is not designed under the fine process technology. As a result, the wiring length of transmission lines is roughly the same as that in the fine-process unadopted LSI. Hence, the parasitic resistance and capacitance values increase, reducing the eye pattern.
In other words, the resistance and capacitance of transmission lines increase along with the process becoming finer. therefore, if a signal is transmitted on an on-chip transmission line at further high speed in the conventional scheme, the eye pattern of the traveling signal will no more be secured.
In particular, since the transfer rate of a clock is generally twice as high as the transfer rate of a data signal, the maximum transfer rate will be restricted with the transfer rate of the clock. Also, in the technique disclosed in Patent Document 2, in which the sampled data must be synchronized with the system clock in the receiver-side LSI, it is necessary to distribute the system clock to the receiver-side LSI. This increases the area and power of the semiconductor integrated circuit.